A Study on Reset Pin Connection

We will use the STM32F446 Nucleo board to conduct the study.

NUCLEO-F446RE - STMicroelectronicsSTMicroelectronics

From the schematic, we can observe that both the STM32F446 chip and the STM32F103 chip (used as the ST-LINK debugger) uses a 100nF capacitor between NRST pin and GND. Additionally, the STM32F103 uses an external 100k pull-up resistor.

This matches the recommended reset circuit in the datasheet. $R_{PU}$ is typically 40k.

Here is a simplified circuit diagram of the reset pin circuit. On Nucleo board the optional 100R resistor is not used.

Now we probe the reset pin voltage level. When the reset button is pressed, the reset pin drops to 0V immediately, and after the button is released, the voltage gradually raises back.

The input Schmit trigger has a high level of 0.7 * VDD, which when VDD is 3.3V, the trigger will detect signal voltage > 2.3 V as a valid high signal. The reset signal takes 5.3 ms after the button release to release the chip from reset state.

The capacitor also functions as a power-on-reset. Here, yellow channel probes the reset voltage, and magenta channel probes the 3V3 voltage. The MCU is released from reset after 59.4 ms after the board is powered on (most of the time is controlled by the ST-LINK debugger), which gives sufficient time for components on the chip to properly initialize.