FT-LINK FTDI Debugger Design Considerations

Signal Mapping for FT2232H

	Pin #
ADBUS0	16	TCK
ADBUS1	17	TDI
ADBUS2	18	TDO
ADBUS3	19	TMS
ADBUS4	21	JTAG Buffer Control
ADBUS5	22	Target present
ADBUS6	23	TSRST in
ADBUS7	24	RTCK
ACBUS0	26	TRST
ACBUS1	27	TSRST
ACBUS2	28	TRST buffer enable
ACBUS3	29	JTAG LED
BDBUS0	38	TXD	connect to device RXD
BDBUS1	39	RXD	connect to device TXD
BDBUS2	40	RTS
BDBUS3	41	CTS
BDBUS4	43	(CK_RST)
BCBUS3	54	RXLED	Active low
BCBUS4	55	TXLED	Active low

PMOD Header Pinout

FT header

Square Pad	1 - 1 TDO	7 - 5 TDI
	2 - 2 nTRST	8 - 6 TMS
	3 - 3 TCK	9 - 7 nSRST
	4 - 4 TXD	10 - 8 RXD
GND Row	5 - GND	11 - GND
VCC Row	6 - VCC	12 - VCC

TileLink header

Square Pad	1 - TL_CLK	7 - CLK_EXT
	2 - TL_IN_VAL	8 - TL_OUT_VAL
	3 - TL_IN_RDY	9 - TL_OUT_RDY
	4 - TL_IN_DAT	10 - TL_OUT_DAT
GND Row	5 - GND	11 - GND
VCC Row	6 - VCC	12 - VCC