-T.K.- Lab Notes
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    • Recoil FOC Motor Controller
      • 0x00. Theory of Operation
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      • Setting up Recoil USB-CAN Adapter - Ubuntu
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      • NVIDIA Isaac Gym URDF Import Notes
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        • Getting Started with Jetson Using SDK Manager on Ubuntu 22.04
        • Using Jetson AGX Orin with Provided Ubuntu 20.04 System
        • Setting up Common Software on Jetson AGX Orin
        • Solving USB-CAN and USB CH340 Driver Issue on reComputer Mini J4012
        • [Deprecated] Upgrading Jetson AGX Orin to Ubuntu 22.04
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      • Case Study: A Dive Into LeggedGym and RSL-RL Framework
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      • Case Study: Looking into robot_lab
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      • Case Study: No-Mercy Project
        • Python Mouse and Keyboard Interaction in Game Environment
        • Detecting Phara
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      • Gazebo Setup
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      • Setting up ROS on Ubuntu 20.04
      • Setting up ETH ANYbotics/elevation_mapping on Ubuntu 20.04
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      • Setting up ROS 2 Humble Hawksbill on Ubuntu
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      • ROS 2 Issue in Ubuntu with conda
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      • Fixing the Unitree A1 Robot Dog Leg Motor
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  • Electrical
    • A Note on the Polarity of the Famous TT Motor
    • Wiring Pinmap Convention
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    • A Study on Reset Pin Connection
    • Note on CAN Termination Resistor
  • UW
    • Digital-Twin Communication System
    • Unreal Engine Communicate with SteamVR
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    • Humanoid Design Notes
      • Robot Body Ratio Issue
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      • Note on Face Design and Manufacture
  • Workflow Automation
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      • Setting up Home Assistant on Raspberry Pi to Control Zigbee IoT Devices
      • Update Sonoff Zigbee 3.0 USB Dongle Plus (CC2652P)
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Powered by GitBook
On this page
  • Installation
  • Step 1. Install conda
  • Step 2. Install conda-lock
  • Step 3. Clone Chipyard
  • Step 4. Configure Chipyard
  • Running RTL Simulation
  • Step 1. Preparing the Environment
  • Step 2. Build the RISC-V binaries
  • Step 3. Running the Simulation
  • Step 3. Examine Waveform
  • Prototype the design on FPGA
  • Step 1. Source the tool scripts
  • Step 2. Building Bitstream
  • Debugging
  • Debug the design with JTAG

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  1. RISC-V / SoC

Quick Start With Chipyard on Ubuntu or WSL

Last updated 4 months ago

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Note:

The following tutorial content is tested on Ubuntu 20.04, Ubuntu 22.04, and WSL 2.0 on Windows 10 systems with Chipyard release 1.10.1

Installation

Step 1. Install conda

Chipyard uses to manage the development environment and packages.

Download Conda from the miniforge .

Select the corresponding Miniforge3 version and download the file ending with ".sh".

After download, we need to mark the script as executable.

chmod +x ~/Downloads/Miniforge3-24.11.0-0-Linux-x86_64.sh

Then, execute the script.

~/Downloads/Miniforge3-24.11.0-0-Linux-x86_64.sh

Follow the installation prompt. The program will prompt you to input the installation location. Here, we are using /home/tk/Documents/miniforge3.

After installation, it will ask whether to execute conda init. Enter "yes" to the prompt.

Conda is now installed on the system.

Note:

After installing conda, the conda path is not added to the PATH environment variable of the current terminal.

If the conda: command not found error occured, open a new terminal (or source ~./bashrc).

Step 2. Install conda-lock

Chipyard also requires the conda-lock module. Install conda-lock by executing the following commands.

conda install -n base conda-lock==1.4.0
conda activate base

Step 3. Clone Chipyard

Open terminal in a known location. Here, we will use the directory /home/tk/Desktop/. In the terminal, execute the following command.

git clone git@github.com:ucb-bar/chipyard.git

Step 4. Configure Chipyard

By default, chipyard setup script initializes/installs things in the following order:

  1. Conda environment

  2. Chipyard submodules

  3. Toolchain collateral (Spike, PK, tests, libgloss)

  4. Ctags

  5. Chipyard pre-compile sources

  6. FireSim

  7. FireSim pre-compile sources

  8. FireMarshal

  9. FireMarshal pre-compile default buildroot Linux sources

  10. Runs repository clean-up

To execute the setup script, run the following command.

./build-setup.sh riscv-tools --use-lean-conda

On older chipyard versions, do this instead:

./build-setup.sh riscv-tools -s 6 -s 7 -s 8 -s 9 --force

The --force flag is used to skip the confirmation prompt, which is buggy on some terminals.

The set up process will take around 10-30 minutes, depending on the system configuration. After the script is finished, Chipyard is initialized and is ready to be used.

Running RTL Simulation

Step 1. Preparing the Environment

On Ubuntu, we will use the open-source Verilator to simulate.

We don't need to do anything special to use Verilator. Just remember to source the env.sh script.

source $chipyard/env.sh

Use the following script to source vcs and other related tools.

source /ecad/tools/vlsi.bashrc

On BWRC machine, we need to source the VCS simulator path. This can be done by executing the following commands.

export VCS_HOME=/tools/synopsys/vcs/S-2021.09-SP1-1/
export VERDI_HOME=/tools/synopsys/verdi/S-2021.09-SP1-1/
export VCS_64=1
export PATH=$VCS_HOME/bin:$VERDI_HOME/bin:$PATH

Alternatively, run the following all-in-one script

source /tools/C/chiyufeng/documents/vcs_env.sh

If running into license issues, try running the following command

source /tools/flexlm/flexlm.sh

If running into JDK_HOME issue(JDK/lib/tools.jar not found), try the following command

export JDK_HOME=/usr/lib/jvm/java-1.8.0/

Step 2. Build the RISC-V binaries

To build simulation code:

# inside chipyard directory
cd ./tests/
make

Step 3. Running the Simulation

Then, we go to the corresponding simulator folder and run the simulation.

cd $chipyard/sims/verilator/

Running a simple RocketConfig simulation

make run-binary CONFIG=RocketConfig BINARY=../../tests/hello.riscv

Running a simulation and generating waveform

make run-binary-debug CONFIG=RocketConfig BINARY=../../tests/hello.riscv timeout_cycles=10000

timeout_cycles can be set to a small value to make the waveform dump process faster.

With fast memory loading

make run-binary CONFIG=RocketConfig BINARY=../../tests/hello.riscv LOADMEM=1

cd $chipyard/sims/vcs/

Running a simple RocketConfig simulation

make run-binary CONFIG=RocketConfig BINARY=../../tests/hello.riscv

Running a simulation and generating waveform

make run-binary-debug CONFIG=RocketConfig BINARY=../../tests/hello.riscv timeout_cycles=10000

timeout_cycles can be set to a small value to make the waveform dump process faster.

cd $chipyard/sims/vcs/

Dispatch the job on ee194 queue

bsub -q ee194 -Is -XF make run-binary CONFIG=RocketConfig BINARY=../../tests/hello.riscv

Dispatch the job on ix queue

bsub -q ??? -Is -XF make run-binary CONFIG=RocketConfig BINARY=../../tests/hello.riscv

Step 3. Examine Waveform

Launch verdi to examine the waveform.

verdi -ssf <fsdb file>

verdi -ssf ./sims/vcs/output/chipyard.harness.TestHarness.REFV256D128ShuttleConfig/tests.fsdb 

Quick Reference:

Ctrl + W: add to current waveform

Prototype the design on FPGA

Step 1. Source the tool scripts

Use the following command to add vivado to PATH

source ~/Documents/Xilinx/Vivado/2024.1/settings64.sh
source /ecad/tools/xilinx/Vivado/2023.2/settings64.sh
source /tools/xilinx/Vivado/2022.2/settings64.sh

Step 2. Building Bitstream

# in chipyard folder
cd ./fpga/

make SUB_PROJECT=arty100t bitstream

Debugging

Debug the design with JTAG

Conda
release page